The operational speed of modern computers is extremely important because of the very large and complex algorithms that computers are required to process within a very short space of time. In the past, computers having the fastest operational speed have typically used emitter-coupled logic or ECL, although recently the operational speed of CMOS logic devices has tended to improve to the point where CMOS logic devices are equally as fast as ECL devices. An advantage of CMOS logic devices is the high degree of integration attainable using such structures. A disadvantage of ECL is the substantial power consumption during circuit operation due to the necessity of biasing the semiconductor devices in a linear operating region. CMOS logic devices in contrast, have a much lower power consumption. Notwithstanding the advances in CMOS performance, it still remains necessary for CMOS circuits to interface with existing "peripheral" ECL circuits for reasons of compatibility. In order to achieve compatibility, a voltage level shifting circuit is required to convert a set of ECL logic voltage levels (approximately (-0.9) volt for a logic high and (-1.7) volts for a logic low) to a set of CMOS logic voltage levels (typically greater than 2.20 volts for a logic high and less than 0.8 volt for a logic low).
Logic level shifting circuits are required to have stringent circuit specifications to achieve optimum speed performance. For example, it is necessary to maintain a specified voltage differential between a defined ECL logic high and a defined ECL logic low with small variation. The voltage differential is also required to be substantially invariant with temperature and immune to electrical noise. A further requirement of the voltage level shifting circuit, for implementation in CMOS technology, is low power consumption and high operational speed.
A known logic level shifting circuit is taught by B. L. Morris in U.S. Pat. No. 4,943,741 entitled "ECL/CML Emitter Follower Current Switch Circuit". An advantage of the circuit described by B. L. Morris is the reduction in power consumption which is attained by relaxation current switching. The relaxation current is provided to enhance the operational speed of the emitter follower and is switched off during certain periods of operation when the relaxation current is not required. A disadvantage of this circuit, however, is the relatively slow switching speed due to a cross-coupling of voltages in a flip-flop type of circuit. The delay time occurs because the cross-coupled voltages have to overcome the barrier potential or cutin voltage of two semiconductor devices.